The AX88196B is a non-PCI Ethernet controller with MII for the Embedded Ethernet applications. The AX88196B supports 8/16-bit SRAM-like host interface, providing a glue-less connection to most common embedded MCUs. The AX88196B integrates on-chip Fast Ethernet MAC and PHY, which is IEEE802.3 10Base-T and IEEE802.3u 100Base-TX compatible and 8Kx16 bits embedded SRAM for packet buffering to accommodate high bandwidth applications. The AX88196B has a wide array of features including support for Twisted Pair Crossover Detection and Auto-Correction, Wake-on-LAN power management and IEEE 802.3x and back-pressure flow control. The programming of AX88196B is simple and compatible with NE2000, so the users don't need any modification and can easily port the software drivers to many embedded systems very quickly. Combining these features with ASIX's free TCP/IP software stack for 8-bit microcontrollers, AX88196B provides the best Ethernet solution for embedded networking applications. High-performance non-PCI local bus Supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series CPU and ISA bus SRAM-like host interface (US Patent Approval), easily interfaced to most common embedded MCUs Embeds 8Kx16 bits SRAM for packet buffers Supports Slave-DMA to minimize CPU overhead Supports burst-mode read for highest performance applications Interrupt pin with programmable Hold-off timer Single-chip Fast Ethernet controller Compatible with IEEE802.3, 802.3u standards Integrates Fast Ethernet MAC/PHY transceiver in one chip Supports 10Mbps and 100Mbps data rate Supports full and half duplex operations Supports 10/100Mbps N-way Auto-negotiation operation Supports twisted pair crossover detection and auto-correction (Auto-MDIX) Supports IEEE 802.3x flow control for full-duplex operation Supports back-pressure flow control for half-duplex operation Provides optional MII interface for external 100BASE-FX Ethernet PHY, HomePNA PHY or HomePlug PHY Supports Wake-on-LAN function to reduce power by following events Detection of a change in the network link state Receipt of a Magic Packet Receipt of a MS wakeup frame NE2000 register level compatible instruction Detection performance can be enhanced with only a minor host driver modification from original NE2000 driver Supports EEPROM interface to store MAC address (Opitional) Supports up to 2 (out) /1 (in/out) General Purpose pins Supports LED pins for various network activity indications Integrates voltage regulator and 25MHz crystal oscillator 0.18um CMOS process. 3.3V power supply with 5V I/O tolerance 100-pin LQFP , RoHS package Operate over 0 to +70 °C or -40 to +85 °C temperature range

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