Video interfaces


We are offering individual support and technical know-how combined with competitive pricing and reliable long-term supply on Interconnectivity SoCs for HDMI Repeater,  HDMI Receiver / Transmitter, MHL ,SRE,  MIPI, DP/ eDP, IDP, LVDS/ cLVDS, OSD, DVI & HDCP, HDMI ARC, Controller/ MCU

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The EP387A supports dual LVDS links transmission between the host and the flat panel display up to QXGA resolutions. The transmitter converts 48 bits (24-bit color, dual pixel) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signal) data streams. At a maximum input clock rate of 112MHz in the dual pixel mode, each LVDS differential data pair speed is 784Mbps, providing a total throughput of 5.4Gbps. Two additional modes are supported. One of them converts 24 bits (24-bit color, single pixel) data input into dual LVDS links and the input clock rate can be up to 165MHz. The other mode converts 24 bits data input into single LVDS link in order to support the inter-operability with the conventional LVDS application. The configurable pre-emphasis feature is provided to support additional output strength to reduce the cable loading effects. The EP387A provides a second LVDS output clock pair. Both LVDS clocks pairs are identical. This feature supports backward compatibility with the previous generation of single pixel LVDS transmitter. The second clock allows the transmitter to interface to panel using a „dual pixel“ configuration of two 24-bit or 18-bit LVDS receivers. Supports SVGA through QXGA resolutions • Support 32.5MHz to 112/170MHz clock rates • Up to 5.4Gbps bandwidth • Pre-emphasis reduces cable loading effects • Programmable Interface to timing controller, dual-in/dual-out, single-in/dual-out and single-in/single-out. • Cycle-to-cycle jitter rejection • 5V tolerant on data and control input pins • Programmable data and control strobe select • Compatible with ANSI/TIA/EIA-644 LVDS standard • Compatible with National DS90C387A • Single 3.3V CMOS design • 100-pin LQFP (Pb Free, compliant to JEDEC/IPC J-STD-006)

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