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Description

The AX88613 is a single-chip 3-port 10/100M Ethernet Switch controllers featuring a 3-port switching fabric with QoS priority management, three 10/100M MACs, two 10/100M PHYs, and MII host interface. The built-in switching fabric in the AX88613 supports non-blocking wire-speed forwarding and offers an advanced switch feature set that includes tag/port-based VLAN, spanning tree, rate control, port security, port mirroring, IGMP snooping, MIB counters and four priority queues for QoS functions including Port-Based, 802.1p VLAN, IPv4 TOS and IPv6 COS to prioritize voice, video, audio and data traffic delivery. The AX88613 have integrated a voltage regulator and provide support for programmable I/O voltage options of 3.3V/2.5V/1.8V to enable a highly optimized system design. As semiconductor designs migrate to advanced process geometries like 90nm, 65nm, 45nm and beyond, many of today's higher performance ASICs, SoCs and FPGAs require lower I/O voltages. The AX88613 combine the benefits of high integration and small form factor making them ideal single-chip solutions for designing high performance, QoS-aware and cost effective 2-port Ethernet functions for embedded system applications such as VoIP phone/ATA adapters, surveillance IP cameras, next-generation IP-STB/IPTV, industrial controller/network sensors, port redundancy/port monitoring and Single Board Computers (SBC). 3-port 10/100M Ethernet Switch integrated with two 10/100M PHYs, three MACs, a switching fabric, a packet buffer memory and a configurable MII/Rev-MII or RMII/Rev-RMII interface for the 3rd port access from external device Fast Ethernet MAC/PHY IEEE 802.3 10Base-T/100Base-TX compatible Supports full-duplex operation with IEEE 802.3x flow control and half duplex with backpressure 10/100M PHY supports twisted pair crossover detection and auto-correction (HP Auto-MDIX) Supports Wake-on-LAN by Microsoft Wakeup Frame, Magic Packet and link status change detection Switching Fabric Performs non-blocking wire-speed forwarding and filtering Embeds 32KB SRAM for packet buffering Supports broadcast storm filtering Support per queue and per port ingress and egress programmable rate limit control Integrates two-way Address-Lookup engine and table for 1K MAC addresses Supports Routing Table/IGMP/VLAN Table access through SPI read/write operation Supports 802.1D Spanning Tree Protocol and 802.1w Rapid Spanning Tree Protocol QoS Supports Quality-of-Service for port-based, 802.1p VLAN and IPv4 TOS/IPv6 COS packets with four priority queues Supports RFC2475 DiffServ-based VLAN Supports up to 3 VLAN groups for port-based VLAN and 16 VLAN entries for 802.1Q tag-based VLAN functions Supports Double tagging 802.1Q-in-802.1Q function for WAN access Security Supports ingress port security mode, incoming packets with unknown source MAC address could be dropped Supports eight Security MAC Registrations Supports 802.1X port-based Authorization Multicast Supports GMRP/GVRP/GARP packet snooping Support IPv4 IGMP and IPv6 ICMP/MLD (Multicast Listener Discovery) Snooping Supports up to 1K Multicast Group (shared with L2 MAC table) Supports eight IGMP Multicast IP address snooping Monitoring Supports RMON group 1,2,3,9 counter (RFC1213) Supports Ethernet-like MIB counter (RFC 1643) Supports Bridge MIB counter (RFC 1493) Egress/Ingress Port Mirroring Sniffer functions: Source/Destination Port DA/SA VLAN ID Ethernet Packet Type IPv4/IPv6 Protocol IPv4/IPv6 TCP/UDP Port Number Optional Interfaces Supported: MII or Reverse-MII RMII or Reverse-RMII Optional serial EEPROM SPI Single 3.3V power supply with options for 1.8V, 2.5V and 3.3V I/O voltage support Integrates an on-chip voltage regulator requiring only a single power supply of 3.3V Integrates an on-chip oscillator and PLL requiring only a 25MHz crystal to operate Integrates on-chip power-on reset circuit 80-pin E-PAD LQFP RoHS compliant package Operating temperature range: 0°C to +70°C

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